RTL Design Engineer

Primary Skill: RTL Design

Work Location: Kochi (Kerala)

Exp: 2 to 6 Years

Required Skills

• Experience with VHDL, Verilog or SystemVerilog for HDL design.
• Knowledge of FPGA design environments including Xilinx Vivado, Intel Quartus & Lattice Diamond.
• Thorough knowledge of FPGA architecture including experience with advanced floor-planning and timing closure techniques.
• Experience with SoC bus interconnect protocols such as AXI4, streaming AXI and AHB.
• Experience with industry-standard high-speed interfaces such as DDR4, 10/40/100 GbE, PCIe, Interlaken, JESD and Aurora.
• Experience with FPGA bring-up, lab debugging, and system validation of complex FPGA designs.
• Experience in wireless communication, DSP implementation, High-Speed Digital Interface Design, Memory Management, and SoC Platforms is good to have.
• Familiarity with embedded software/firmware design, especially in complex debugging of on-target SW/HW interaction.
• Experience with Xilinx UltraScale/UltraScale+ FPGA families and SoC-based architectures (NIOS/Microblaze/ARM cores)

If interested, please share your updated profile with pravin.cp@vvdntech.in