S - Front-End Integration Engineer｜全球知名CPU、GPU大廠（台北／新竹）

【工作內容】
1. Responsible for front-end implementation and integration of high-performance ASIC / SoC IP, with a strong focus on logic synthesis, physical implementation support, and ECO activities.
2. Perform and optimize logic synthesis to meet timing, area, power, and design quality requirements.
3. Support physical implementation activities and work closely with Physical Design teams on placement-related, timing, congestion, and implementation issues.
4. Perform static timing analysis (STA), analyze timing violations, and support timing closure across different implementation stages.
5. Responsible for functional and timing ECO implementation, including ECO generation, validation, and related design updates.
6. Perform formal equivalence / LEC checks to ensure design correctness after synthesis and ECO changes.
7. Perform RTL and design quality checks, including Lint, CDC / RDC, and other front-end signoff activities.
8. Maintain and execute IP regression and implementation flows to ensure design quality and delivery readiness.
9. Collaborate with global IP, SoC integration, RTL Design, and Physical Design teams to support Tile / subsystem integration.
10. Support IP / SoC tapeout activities and resolve implementation-related issues throughout the design cycle.
11. Develop or enhance scripts and automation to improve synthesis, ECO, timing analysis, and implementation efficiency.

【職務條件】
1. Minimum 3 years of experience in Digital ASIC / SoC front-end implementation, design implementation, or related fields.
2. Strong knowledge of Verilog / SystemVerilog and digital ASIC design concepts.
3. Hands-on experience in logic synthesis.
4. Hands-on experience in ECO implementation, including functional and/or timing ECO.
5. Experience working with physical implementation / Physical Design flows, with good understanding of the interaction between front-end design and backend implementation.
6. Good knowledge of Static Timing Analysis (STA) and timing closure concepts.
7. Strong debugging, problem-solving, and cross-functional collaboration skills.
8. Experience with Formal Verification / LEC or equivalent methodology.
9. Familiarity with front-end quality checks such as Lint, CDC / RDC, and design regression.