S - Power / Low Power ASIC Design Engineer｜全球知名CPU、GPU大廠（台北／新竹）

【工作內容】
•Perform RTL and gate-level power estimation, analysis, and profiling for CPU / GPU / SoC designs.
•Use PrimePower RTL (PPRTL) and PrimeTime PX (PTPX) to analyze power consumption across different design stages and operating scenarios.
•Identify power-critical blocks and provide RTL / design-level optimization recommendations.
•Work with RTL Design, Front-End Integration, Physical Design, Architecture, and Verification teams to improve Power, Performance, and Area (PPA).
•Support power analysis across pre-synthesis and post-synthesis / netlist stages.
•Analyze switching activity, clocking, power distribution, and design behavior to identify power optimization opportunities.
•Support low-power design implementation and analysis, including UPF-based designs where applicable.
•Develop scripts and automation to improve power analysis and reporting efficiency.

【職務條件】
•Minimum 2 years of experience in ASIC / SoC design, power analysis, Physical Design, or related front-end implementation.
•Hands-on experience with PrimePower RTL (PPRTL) and PrimeTime PX (PTPX).
•Good understanding of ASIC / SoC design flow from RTL through synthesis and gate-level implementation.
•Understanding of power fundamentals, including dynamic power, leakage power, switching activity, and clock-related power.
•Familiarity with Verilog / SystemVerilog and RTL design concepts.
•Familiarity with netlist, UPF, SPEF, synthesis, and timing concepts.
•Scripting experience with Python, TCL, Perl, or Shell.