Sr. Design Engineer 2
Posted Updated
Description
<h2><strong>Key Responsibilities</strong></h2><ul>
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<p>Develop micro-architecture specifications based on system requirements.</p>
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<p>Design and implement RTL using Verilog/SystemVerilog.</p>
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<p>Perform RTL coding, linting, CDC checks, and synthesis.</p>
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<p>Work closely with verification teams for testbench support and debug.</p>
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<p>Participate in design reviews and provide technical solutions.</p>
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<p>Perform block-level and SoC-level integration.</p>
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<p>Support STA, DFT, and physical design teams during implementation.</p>
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<p>Analyze and debug functional and timing issues.</p>
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<p>Ensure design meets power, performance, and area (PPA) targets.</p>
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<p>Collaborate with cross-functional teams including firmware and validation.</p>
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</ul><hr /><h2><strong>Required Skills & Qualifications</strong></h2><ul>
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<p>5–8 years of hands-on experience in RTL design for ASIC/SoC.</p>
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<p>Strong expertise in Verilog/SystemVerilog.</p>
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<p>Experience in micro-architecture and high-speed digital design.</p>
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<p>Good understanding of synthesis, STA, CDC, and low-power design concepts.</p>
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<p>Experience with industry-standard EDA tools (e.g., Synopsys, Cadence, Mentor).</p>
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<p>Strong debugging and problem-solving skills.</p>
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<p>Knowledge of scripting languages (Perl/Python/TCL) is a plus.</p>
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<p>Familiarity with AMBA protocols (AXI/AHB/APB) preferred.</p>
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<p>Experience in IP integration and SoC architecture.</p>
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</ul><hr /><h2><strong>Preferred Qualifications</strong></h2><ul>
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<p>Experience in high-speed interfaces (PCIe, USB, Ethernet, DDR, etc.).</p>
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<p>Exposure to low-power design techniques (UPF/CPF).</p>
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<p>Experience in 7nm/5nm or advanced technology nodes is an advantage.</p>
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<p>Knowledge of FPGA prototyping is a plus.</p>
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</ul><hr /><h2><strong>Education</strong></h2><p>
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<p>B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / VLSI / related field.</p></li></ul>