【新竹】ASICS Design Engineer, Senior to Staff (3093368)

【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】

Please apply directly on Qualcomm Career Site via link below, and attach your English resume for further review. Thank you!

https://qualcomm.wd12.myworkdayjobs.com/zh-CN/External/job/Hsinchu-City-TWN/ASICS-Design-Engineer--Senior-to-Staff_3093368

【General Summary】
Education:
MS/BS in EE (MS preferred).

【Experience】
2–10 years ASIC design experience. Experience in merchant silicon or switching ASIC (e.g., Broadcom/Marvell/Realtek/MTK networking chips) is desirable.

【Requirements】
Familiar with ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow.
Strong expertise in ASIC FE design flow (RTL, simulation, STA, integration).
Familiarity with Ethernet switching concepts, such as:

• L2/L3 forwarding, bridging, routing
• Packet processing pipelines
• Basic QoS (queuing, scheduling)

Hands-on experience in Ethernet switching / networking ASICs, including:

• Packet classification and forwarding pipelines
• Buffer management and QoS mechanisms
• Knowledge of protocols (Ethernet, VLAN, TCP/IP, tunneling, etc.)

Knowledge of AXI/NoC, PCIe or high-speed interfaces is a plus.
Ability to independently drive complex design tasks.
Strong debugging and system-level problem-solving skills.
Scripting skills (C/C++, Tcl, Perl) preferred.
Excellent teamwork, interpersonal and communication skills.
Fluent in Chinese and English both verbal and written.
Ability to work in stressful situations with tight schedules to meet.

Description of Function & Responsibility:
Implement RTL design, synthesis, and timing closure for networking datapath/control logic.
Participate in SoC integration with focus on Ethernet switch subsystems.
Lead design and delivery of key subsystems in Ethernet switch ASICs, driving architecture-aligned implementation and optimization.
Own micro-architecture and RTL design of networking blocks (e.g., forwarding engine, parser, traffic manager).
Drive subsystem integration, performance tuning, and power optimization.
Debug functional and performance issues across design, DV, and validation teams.
Collaborate with architecture, firmware, and validation teams to support chip bring-up.
Work with architecture teams to refine Ethernet switch features and scalability.
Mentor junior engineers and guide best engineering practices.