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Samsung Semiconductor

Principal Engineer, Hardware Emulation

New North AmericaPrincipal H-1B sponsor history

A senior engineer who owns and maintains hardware emulation infrastructure (Palladium/Zebu platforms) for pre-silicon validation of mixed-signal networking SoCs — bringing up emulation platforms, developing monitors/checkers and workflows, debugging emulation performance and design issues, and working with simulation, firmware, and software teams. Onsite in San Jose.

AI Candidate Experience Firmware IoT Networking +5 skills

219K – 351K $

Intuitive Surgical

Staff Electrical and Electronic Design Engineer - Future Forward

New North AmericaStaff Licensed UK sponsor H-1B sponsor history

The Future Forward group within Intuitive Surgical is searching for a Staff Electrical and Electronic Design Engineer to architect, design, and bring up the electronic hardware behind next-generation robotic and vision…

Accessibility Altium Automation Ethernet Firmware +14 skills

Microarchitect and RTL Designer - Compute

New HybridNorth AmericaFull-time

Own micro-architecture and RTL for the compute subsystem of MatX's AI accelerator chips — from spec through area/timing closure, design freeze, and tapeout — collaborating with verification, DFT, and physical design teams. Core tech: SystemVerilog, Bluespec, Python, C/C++, synthesis and sign-off flows. Mountain View HQ or remote.

AI C++ Haskell Machine Learning Python +2 skills

175K – 600K $

Technical Lead - Fellow Hardware Engineer, NPU

New North AmericaFull-timeLead

Fellow-level technical lead owning NPU (AI accelerator) architecture and integration into an automotive SoC at CARIAD, Volkswagen Group's software company. Day to day: setting the NPU technical roadmap, leading architecture/RTL/verification decisions, and driving the chip from design through silicon and production readiness; requires deep ASIC/SoC expertise.

Acceptance Criteria AI Asic C++ Cryptography +12 skills

287K – 362K $

Emulation & FPGA Prototyping Engineer

New North America

Owns emulation and FPGA prototyping for SoC programs at Voltai — building emulator/FPGA platforms, mapping designs with partitioning and timing closure, enabling early software bring-up, and debugging system-scale hardware/software issues while generating data to train Voltai's AI models. Key tools: Palladium/ZeBu/Veloce/HAPS, SystemVerilog, Vivado/Quartus, Python/Tcl/C++.

AI Automation C++ Firmware FPGA +5 skills

RTL Design Engineer

New North America

Design and own RTL for production silicon at Voltai — microarchitecture and SystemVerilog implementation for IP blocks, driving lint/CDC, synthesis, and timing closure, and debugging across simulation, emulation, and silicon, while helping train Voltai's AI to write and review chip designs.

AI Ethernet PCIe Python Rtl +3 skills

Semiconductor_ (Malaysia)_ Sdn Bhd Taiwan Branch

Design Verification Manager

New On-siteNorth America

Leads a geographically distributed IC design verification team at Semtech, building SystemVerilog/UVM testbenches and verification plans for mixed-signal chip blocks, driving coverage closure, regression testing, and mentoring engineers. Hybrid role in San Diego or San Jose; 10+ years of design verification experience required.

Automation CI/CD Firmware I2c Perl +7 skills

116K – 216K $

Advanced Micro Devices, Inc

Design Verification Engineer

New North America

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

AI Automation Bash Cloud C++ +13 skills

Graduate FPGA Engineer (2027 Start)

Open 68d EuropeInternshipJunior Licensed UK sponsor H-1B sponsor history

Designs high-speed hardware solutions (FPGAs) for ultra-low-latency trading systems, collaborating with traders and engineers to optimize network infrastructure and algorithmic trading components using VHDL/Verilog.

AI FPGA Networking SystemVerilog Verilog +1 skills

Electrical Engineer I - FPGA Designer (58060)

New North America

Applied Technical Services, LLC, is a leading provider of critical testing, inspection, certification, and compliance services. The company serves clients across a diverse set of large and stable end markets including…

FPGA SystemVerilog Verilog VHDL

Senior Electrical Engineer - FPGA Designer (58061)

New North AmericaSenior

Applied Technical Services, LLC, is a leading provider of critical testing, inspection, certification, and compliance services. The company serves clients across a diverse set of large and stable end markets including…

FPGA SystemVerilog Verilog VHDL

FPGA Digital Design Engineer

New RemoteNorth AmericaFull-time

This position is listed on behalf of a partner company, which manages all applications and next steps. Our partner is looking for an FPGA Digital Design Engineer based in United States. As an FPGA Digital Design…

AI FPGA Gdpr Root Cause Analysis SystemVerilog +2 skills

RO61 NXP Semiconductors Romania SRL

Digital Verification Senior Manager

New On-siteAPACSenior

Role Summary Lead an SoC verification team developing advanced MPU and MCU products. Own SoC-level verification strategy, planning, execution, coverage closure and sign-off, while building a strong team and…

AI Automation C++ Firmware Iso 26262 +6 skills

达摩院-CPU验证工程师-计算技术

New APAC H-1B sponsor history

CPU verification engineer at Alibaba's DAMO Academy (computing technology) in Chengdu/Shanghai: designs and builds chip- and module-level verification environments, runs functional/integration/low-power and gate-level simulations, debugs failures, and delivers fully verified CPU designs. Core stack: UVM, SystemVerilog, C/assembly, RISC-V/ARM, AMBA.

C++ SystemVerilog Uvm

Senior Silicon Design Verification Engineer, Mixed Signal

New APACSenior Licensed UK sponsor Licensed NL sponsor Denmark Fast-track company

Senior engineer verifying digital and mixed-signal design blocks for Google's custom silicon in consumer hardware products — planning verification strategies, building UVM/SystemVerilog testbenches and coverage, and driving verification through tape-out from offices in New Taipei City or Zhubei, Taiwan.

AI Python SystemVerilog Uvm Verilog

Hardware Engineer

New APAC Licensed NL sponsor

Designs and deploys FPGA-based hardware for ultra-low-latency trading at a global market maker — building systems that parse market data and execute trades in nanoseconds. Core work spans VHDL/Verilog/SystemVerilog, FPGA toolchains like Vivado and Quartus, C++/Python, and performance tuning from transceivers to logic layout.

C++ Ethernet FPGA Machine Learning Networking +5 skills

VivCourt Trading

FPGA Engineer

You will contribute throughout the FPGA development lifecycle, including architecture, verification, synthesis, timing, and integration. You will partner with traders and software engineers to understand requirements,…

Asic C++ FPGA Python SystemVerilog +1 skills

Open Roles at VivCourt

FPGA Engineer

About VivCourt We’re VivCourt, a trading firm like you’ve never seen before. We use our smarts and leading-edge technology to trade on financial markets worldwide, but we're saying no to how it’s always been done.…

Asic C++ FPGA Python SystemVerilog +1 skills

Velaura AI, Inc.

Senior Design Verification Engineer

New On-siteAPACSenior

Develops and executes verification strategies and environments for complex SoC hardware — building UVM/SystemVerilog testbenches, assertions, formal and emulation flows, verifying compute, memory, and interconnect blocks, and supporting emulation, FPGA prototyping, pre-silicon bring-up, and post-silicon debug.

C++ FPGA Prototyping QoS Root Cause Analysis +2 skills

Velaura AI, Inc.

Design Verification Engineer CPU

New On-siteAPAC

Verification engineer for a custom CPU: owns functional verification from test planning through coverage closure — building SystemVerilog/UVM environments, writing C/C++ instruction-level stimulus, verifying memory ordering, coherence, and performance, and supporting emulation, FPGA prototyping, and pre-silicon software bring-up.

C++ FPGA Prototyping Root Cause Analysis SystemVerilog +1 skills