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Designs secure, cost-sensitive FPGA-based products from architecture to production, collaborating cross-functionally on defense systems with Zynq UltraScale+ MPSoC and Vivado tools.
Senior Embedded Software Engineer designing and implementing embedded software for software-defined radio platforms, working with C/C++, Linux, ARM, and RF hardware on-site in Los Angeles.
Leads research in open-source processor/accelerator architectures (RISC-V, AI) using Verilog/SystemVerilog and EDA tools, publishing findings and mentoring junior researchers.
The Senior Electronics Engineer will lead the design and development of complex instruments for the defence and security sectors, managing the full product lifecycle from concept to prototype. The role requires expertise in HDL languages and FPGA toolchains to develop advanced communications, RADAR, and detection technologies.
This is an internship role for a Master's student to support the FPGA verification team in developing and implementing verification solutions for next-generation Altera products. The role involves working with HDL languages, scripting, and FPGA tools to ensure high-quality delivery of IP and hardware products.
The Senior Software Engineer will develop internal tools and automation to optimize silicon design workflows within Arm's Solutions Engineering group. The role focuses on building robust software systems using Python to support complex hardware engineering processes.
The Semiconductor Software Engineer designs and builds software tooling, firmware, and infrastructure to support semiconductor design, verification, and post-silicon validation workflows. The role involves working with C, C++, and Python to optimize compute-intensive processes and data pipelines for silicon characterization.
System Test Engineer verifying next-generation AI/ML neural network hardware accelerators at Arm, designing test automation and working with emulation platforms (ZeBu/Palladium/Strato) and RTL (SystemVerilog).
Leads SoC design and RTL development for advanced sensor platforms, defining architecture, integrating subsystems, and driving cross-functional teams from concept to silicon.
Join Solidigm’s visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help shape the future of memory technology. Job responsibilities include, but not limited to: Architect, design, and verify…
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
Design Verification Engineer at Bitdeer in Singapore, responsible for verifying complex digital ASIC designs using UVM, SystemVerilog, and industry tools to ensure functional correctness and silicon quality.
Leads a team to verify complex ASIC/SoC designs for Bitcoin mining and AI cloud hardware, using UVM, SystemVerilog, and protocol knowledge (AXI, NoC, RISC-V) to ensure silicon quality.
An internship designing ultra-low-latency FPGA hardware systems for trading platforms, using SystemVerilog, C++, and Python to optimize market data processing and order execution.
Design and deploy ML models directly onto custom hardware, co-architecting solutions with traders and engineers while optimizing for latency and resource constraints.
Design and verify custom ASICs for ultra-low-latency trading systems using SystemVerilog, C++, and Python, collaborating with hardware, software, and trading teams.
Hardware Engineer Intern contributing to FPGA development and hardware improvements at a global trading firm, using VHDL/Verilog and collaborating with trading and tech teams.
This graduate role involves working with verification experts to verify DDR subsystems using SystemVerilog, UVM, and formal verification techniques. The engineer will write tests, develop testbench components, and track verification quality metrics like code and functional coverage.
Senior Staff SOC DFX RTL Design Engineer at AMD's Radeon Technologies Group responsible for planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) for next-generation microprocessors, collaborating with architecture, IP design, and physical design teams.
RTL/SOC integration design engineer at AMD Hyderabad, responsible for ASIC design in sub-20nm nodes using Verilog/SystemVerilog, timing analysis, low-power design, and SOC verification tools.
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