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Designs and implements RTL code and micro-architectures for digital IPs and SoCs in the automotive domain, following the full ASIC flow.
. We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip…
We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
Design and implement testability features (SCAN, MBIST, BSCAN) for Intel’s WiFi/BT chips, ensuring high test coverage and manufacturability.
Lead the design of next-gen ASIC IP for AI-driven data movement, collaborating across teams to deliver high-performance, secure, and power-efficient silicon solutions for AMD’s server, data center, and embedded products.
Designs and implements GPU hardware in Verilog/SystemVerilog, optimizing for performance, power, and area while collaborating with verification teams.
Role Overview We are looking for a Senior Technical Recruiter – Engineering to help build the engineering organization behind Velaura’s next generation of AI compute platforms. This role will own recruiting across a…
Design Verification Engineer builds and verifies RTL components in Verilog/SystemVerilog to improve AI model training and evaluation workflows, using UVM and LLM-based tools.
Designs and codes RTL for custom silicon subsystems using Verilog/VHDL, integrates IP, and runs simulations and checks to deliver high-performance hardware for Google’s products.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Lead MTS Logic Design Location: Vught, UNAVAILABLE, NL Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Member of Technical Staff Logic Design…
SMTS Logic Design Location: Montreal, UNAVAILABLE, CA Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Member of…
Principal Engineer designs and verifies memory controller IP for DDR/HBM/GDDR DRAM, building SystemVerilog testbenches and coverage-driven regression suites.
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Principal PCIe Logic Design Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our…
PE Logic Design Location: Bangalore, KA, IN Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design…
Designs high-speed datapath and circuit blocks for 3D NAND flash memory, including page buffers and RTL logic, using Verilog and simulations to meet performance specs.
Designs high-speed memory interface chips using Verilog/SystemVerilog, working with RTL, ASIC flows, and post-silicon validation to optimize data speed and security.
Design and verify next-gen high-speed Switch Silicon chips for networking, focusing on power, area, and performance while collaborating with architecture and firmware teams.
We are looking for a Chip Design DFT/Post Silicon Manager to develop the next generation DFT technologies. As a Chip Design DFT/Post Silicon Manager in the DFT team at NVIDIA, you will lead team that transfer our DFT…
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