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Architects and evolves the flight operating-system platform for K2 Space's high-power satellites in Los Angeles: a custom real-time Linux distribution, secure U-Boot boot chain, device trees, and tooling for 20kW+ spacecraft. Core languages are Rust, C/C++, and Python (plus VHDL/SystemVerilog); $160k-$200k + equity.
Design, implement, and verify mission-critical FPGA firmware for K2 Space's high-power satellites — owning RTL architecture in VHDL/SystemVerilog that controls propulsion, attitude control, RF, and power systems, and validating designs via simulation, bench testing, and hardware-in-the-loop testbeds.
Develops and verifies real-time, fault-tolerant flight software for high-power satellites using Rust, C++, and Python, controlling propulsion, attitude, and power systems.
K2 Space is hiring a Senior ASIC Design Verification Engineer to verify the functionality, performance, and robustness of custom silicon for its high-power satellites. Day to day, this means building SystemVerilog/UVM testbenches, writing assertions, running and debugging simulations, driving coverage closure, and managing regressions/CI, plus supporting silicon bring-up.
Hands-on principal-level ASIC design verification role at K2 Space, a satellite manufacturer: the engineer defines verification plans and methodology, builds SystemVerilog/UVM testbenches with assertions and coverage, manages regressions and CI, and supports silicon bring-up for custom silicon in high-power satellite platforms.
Principal Flight Software Engineer at K2 Space in Los Angeles designs and implements real-time, fault-tolerant control software for high-power satellites using Rust, C++, and Python, with responsibilities spanning architecture, subsystem integration, and on-orbit operations.
Design and verify mission-critical FPGA firmware for high-power satellites, implementing real-time control, networking, and RF systems in VHDL/SystemVerilog.
Senior FPGA engineer building hardware prototypes and validating next-gen satellite communications ASICs, from FPGA bring-up to first-silicon debug.
6+ month contract FPGA engineer designing and implementing digital payload code for Kepler's satellites: custom IP, DSP modulation/demodulation for on-board software-defined radios, and embedded processor/peripheral interfaces. Full FPGA flow (simulation, synthesis, place & route, timing closure, hardware testing) using Verilog/SystemVerilog/VHDL on Xilinx Zynq/UltraScale.
Anello Photonics is hiring an FPGA Design Engineer in Santa Clara, CA to design, verify, and bring to production FPGA-based hardware for its next-generation photonic navigation products. Day to day: RTL design and simulation (Verilog/SystemVerilog/VHDL), timing closure, hardware bring-up/debugging, and cross-functional collaboration through production.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
A PhD research internship at IMC Trading in Chicago focused on deploying machine learning onto custom hardware (FPGAs/ASICs) for low-latency ML inference. The intern owns a research project end-to-end, works hands-on with hardware engineers, and leaves behind a prototype or benchmark using tools like PyTorch/TensorFlow, VHDL/SystemVerilog, HLS, hls4ml, FINN, and Vitis AI.
Experienced FPGA developer at Kryptus, a 23-year-old Campinas-based cryptography company building HSMs, high-performance network encryptors, and quantum key distribution systems. Day to day: design RTL in SystemVerilog/VHDL for 100G/200G packet processing and hardware crypto cores (AES-256-GCM, post-quantum), close timing on AMD UltraScale+ devices, and write testbenches supporting FIPS 140-3 cert
Senior software engineer in Astera Labs' AppliedAI org building LLM-powered agents to accelerate RTL design, static/lint checking, and formal verification for the company's AI connectivity semiconductor products. Day-to-day involves Python, LLM fine-tuning, RAG, and multi-agent systems integrated with CAD/EDA flows, collaborating with RTL, DV, formal, and CAD teams.
ASIC Design Verification engineer building UVM testbenches and driving IP/sub-system/SoC verification closure for Ethernet and high-speed networking data-center ASICs. Day to day: simulation, formal verification and emulation, coverage closure, debugging failures with design teams. Core stack: SystemVerilog, UVM, Verilog, AXI/APB, Python/C/C++.
Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
Roles and Responsibilities : Design, develop, test, and verify Ethernet-based IP blocks using SystemVerilog and UVM. Collaborate with cross-functional teams to integrate ASIC designs into larger systems. Develop and…
