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Senior ATE Test Engineer

Open 58d North AmericaSenior H-1B sponsor history Canada LMIA employer

Senior ATE Test Engineer at Astera Labs defining SoC test strategy and building ATE test programs and hardware (Advantest 93k) for mixed-signal connectivity silicon, taking products from first samples through high-volume production ramp. Work centers on SerDes production test at 16Gbps+, DFT, high-speed protocols like PCIe/Ethernet/DDR, and C/C++/Python.

AI C++ Ethernet Express.js I2c +6 skills

136K – 170K $

Principal Design Verification Engineer- SerDes/PHY IP

Open 58d North AmericaPrincipal H-1B sponsor history Canada LMIA employer

Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP for its AI connectivity semiconductors. Day to day, this person architects UVM/SystemVerilog verification environments, drives coverage closure through tape-out, and verifies PHY behavior against PCIe Gen 6/7, UALink, UCIe, and Ethernet standards, including analog/mixed-signal

AI Automation Ethernet Firmware PCIe +5 skills

207K – 230K $

Recruiting Coordinator

Open 15d North America

Recruiting Coordinator Reports To: Senior Manager, Human Resources Company Overview: Netlist, Inc. (OTCQB: NLST) is a leading provider of high-performance modular memory subsystems and next-generation storage-class…

Onsite_Hardware Design and Failure Analysis Engineer_ San Jose, CA

NewBe an early applicant On-siteNorth AmericaContract

Title: Hardware Design and Failure Analysis Engineer Location: San Jose, CA (Onsite) Work Arrangement: Onsite Employment Type: Contract Duration: 6 Months Primary Skills: High-Speed System Architecture & Debugging,…

Automation AWS Cloud PCIe Python +2 skills

Technical Program Management Manager

NewBe an early applicant APAC

This is an internal facing role that is highly focused on execution excellence, organizational alignment and on-time delivery of all Zion ASIC designs. This role coordinates complex multi-disciplinary efforts spanning,…

AI GPU PCIe Program Management SerDes

Lead Site Reliability Engineer (SRE)

NewBe an early applicant HybridEuropeFull-timeSenior

WHO WE ARE? WE ARE A GLOBAL LEADER IN ENGINEERING AND IT SERVICES . At ALTEN, we see our specialists as architects—designers of tomorrow’s world . As a leader in engineering and IT services, we support companies in…

AI Bash CI/CD DHCP DNS +8 skills

Senior Hardware Engineer

NewBe an early applicant HybridEuropeSenior

Mission: The SAR Product Team is looking for an experienced and highly motivated Senior Hardware Engineer to lead the design and development of advanced electronic systems for airborne and spaceborne SAR payloads. This…

Ethernet FPGA I2c Oscilloscope Pcb +2 skills

Senior Embedded Engineer

NewBe an early applicant North AmericaFull-timeSenior

Hands-on senior embedded engineer at defense contractor nou Systems in Huntsville, AL, owning prototype hardware end to end: FPGA design (VHDL/Verilog), PCB design (Altium), C/C++ firmware for microcontrollers and SoCs, lab bring-up/debug, and Python test automation for missile defense, sensing, and space programs. In-person role; US citizenship and Secret clearance required.

AI Altium Assembly Automation C++ +31 skills

OSI Systems, Inc

Embedded Software Engineer 3

NewBe an early applicant North AmericaFull-time

Overview Continental Electronics Corporation is a leading provider of RF technologies and innovative solutions with 80 years of proven performance. CEC has experienced significant recent growth and has established…

AJAX Bash Corrective Action C++ Embedded Software +20 skills

Senior Hardware Design Engineer (15172) (Sterling Heights, MI)

NewBe an early applicant North AmericaContractSenior

HRU-Tech is hiring a Senior Hardware Design Engineer (long-term contract-to-hire) in Sterling Heights, MI to design ruggedized electrical circuit boards and I/O hardware, from schematic and PCB design through prototyping, testing, qualification, and production support. Core skills: analog/digital circuit design, PCB layout, hardware debugging, and military EMC/environmental standards.

Corrective Action C++ Ethernet FPGA Microcontrollers +5 skills

60 – 65 $ / hr

FPGA Design Engineer (15095) (Sterling Heights, MI)

NewBe an early applicant North America

FPGA Design Engineer in Sterling Heights, MI developing FPGA designs for video/image processing, control systems, and system interfaces. Involves creating IP in VHDL/Verilog/HLS, using the Xilinx toolchain (Vivado, Vitis), timing closure, verification, and embedded development on Linux and RTOS. Requires a relevant bachelor's degree and 10+ years of experience.

C++ Embedded Software Embedded Systems Ethernet FPGA +9 skills

FPGA Design Engineer (15173) (Sterling Heights, MI)

NewBe an early applicant North America

Designs and supports FPGA firmware (VHDL/Verilog, Xilinx Vivado/Vitis, Zynq UltraScale+ SoC) for high-voltage and I/O hardware on General Dynamics Land Systems military vehicles. Day to day: requirements breakdown, IP integration, timing closure, simulation, and lab debug at the Sterling Heights, MI site.

Ethernet FPGA Git I2c Jira +3 skills

ПАО Сбербанк

Разработчик электроники (Центр Квантовых технологий)

Сбер начинает работу над квантовым компьютером и аналоговыми вычислителями. Мы предлагаем вам присоединиться к команде Центра Квантовых Технологий Сбера, чтобы решать самые интересные задачи на переднем крае науки и…

Altium FPGA PCIe Python SerDes

FPGA Engineer

Open 49d On-siteMENA

Senior FPGA & System Architecture Engineer at Sentrycs (counter-drone security tech) who owns end-to-end hardware architecture on AMD Xilinx RFSoC platforms: translating MATLAB/C++ DSP models into SystemVerilog RTL, building high-bandwidth PCIe/DMA host and GPU interfaces, and leading verification and lab bring-up with Vivado and RF test equipment.

C++ Embedded Software FPGA GPU Linux +5 skills

Semiconductor IP Sales Partner – Europe & UK

Hiring Alert: Semiconductor IP Sales Partner Europe & UK

NewBe an early applicant

📢 Hiring Alert: Semiconductor IP Sales Partner – Europe & UK 📍 Location: Europe & United Kingdom 💼 Engagement: Commission-Only Sales Partner | Non-Exclusive 🧑‍💻 Experience: 5+ Years ✈️ Travel: Willingness to visit…

Business Development PCIe

智能引擎-KV Cache 存储系统开发-杭州

NewBe an early applicant APAC H-1B sponsor history

1. KVCache 核心系统研发，负责 LLM 推理场景下 KVCache 的架构设计与工程实现，优化 KVCache 的内存管理、显存分配与生命周期调度策略，研究并实现 Prefix Cache、Radix Tree Cache 等高效缓存复用机制，提升 Cache Hit Rate。 2. 设计跨机、跨节点的分布式 KVCache 共享与迁移方案，实现 KVCache 在 GPU HBM / CPU DRAM / NVMe…

Ceph C++ CUDA GPU LLM +7 skills

Staff Design Engineer, Networking, Google Cloud

NewBe an early applicant MENAStaff

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…

AI Cloud C++ Ethernet Express.js +7 skills

Kasmo Cloud Solutions

RTL Integration Engineer – PCIe Gen5 To Gen8

NewBe an early applicant On-siteAPAC

RTL Integration Engineer – PCIe Gen5 to Gen8 . Experience required: 8–12+ years in high-speed interface RTL integration. Key skills: PCIe Gen5+ controller and PHY integration, PCIe protocol layers (TL/DL/PHY), LTSSM,…

Graphcore Early Careers

Graduate Hardware Engineer 2027

NewBe an early applicant UKFull-timeJunior

Location: Bristol, UK Salary: £45,000 per annum Start date: September 2027 Applications deadline : Midnight, 29th November 2026 We encourage you to apply early, as we may close applications before the advertised…

AI Ansys Ethernet Firmware I2c +4 skills

數位IC設計資深工程師P2

NewBe an early applicant APACSenior

工作項目： 1. Maintain並開發 USB3、USB4與 PCIe之 DPHY/MAC相關 design. 2. 整合 USB3、USB4、PCIe等 SerDes PHY與 MAC. 應徵條件： 1. 熟悉 USB3.2、PCIe、PIPE4/5等 Spec. 2. 具 USB3.2 or PCIe Gen3/Gen4 DPHY/MAC設計經驗。 3. 具 USB3.2 or PCIe Gen3/Gen4等 PHY…