Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Design Verification Engineer at Cisco in Armenia builds and runs testbenches in SystemVerilog to validate ASIC designs, debug with DVE/Verdi, and script in Tcl/Python/Perl.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
National General is a part of The Allstate Corporation, which means we have the same innovative drive that keeps us a step ahead of our customers’ evolving needs. We offer home, auto and accident and health insurance,…
Design and verify security IP for SoCs, focusing on cryptography, key management, secure boot, and hardware root of trust using UVM, SystemVerilog, and C.
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
Maintains and optimizes NCR Voyix’s virtual server environments, VMware infrastructure, and cloud platforms (AWS/GCP/Azure) while troubleshooting OS, networking, and storage systems for retail and dining clients.
Own and drive PDK/IP infrastructure for Cisco’s hardware platforms, coordinating vendor IPs, standard cells, and PDKs from design through tape-out and post-silicon validation.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Intern firmware engineer writing and testing embedded C/C++ code for storage devices, collaborating with teams to debug and optimize firmware for microcontrollers.
Design and verify custom silicon for Google’s TPU AI accelerators, focusing on management/control subsystems and SoC integration.
Experienced Engineer - FPGA CAD Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Join our Team About this opportunity: You will join the FPGA CAD team to support design and…
Lead a team in Bangalore to define and scale physical design methodologies and CAD flows for Microsoft’s custom silicon (Azure Cobalt and Maia), driving AI-driven automation and first-pass silicon success.
Technical Marketing Engineer creating training, documentation, and demos for AMD’s Vivado FPGA tool suite, validating features and enabling customers through clear technical communication.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Designs and optimizes ASIC chip layouts using Place & Route tools like Cadence Innovus or Synopsys ICC2, focusing on timing, power, and area efficiency.
Build and maintain automated test suites for Nokia’s 5G fixed wireless access devices using Robot/Python, validating performance, security, and stability in a Linux-based CI/CD pipeline.
Verify mixed-signal IPs (e.g., PCIe, USB4/Type-C PHYs) using SystemVerilog/UVM, EDA tools, and scripting to ensure performance and reliability before silicon tape-out.
Designs and deploys secure, high-availability networks for air-traffic and mission-critical systems, leading small teams through integration, testing, and deployment.
Principal Firmware Engineer in Luton designing and auto-generating firmware for complex digital systems using MATLAB, Simulink, Verilog, and FPGA tools.
Lead validation of Cadence’s Sigrity SI/PI/EM simulation tools, designing test plans, automating regressions, and ensuring product quality for high-speed PCB and IC designs.
We couldn't check your fit for this role — add a CV to your profile to see it next time.