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Space is a warfighting domain. True Anomaly seeks those with the talent and ambition to build the technology that secures it. OUR MISSION True Anomaly delivers decisive capabilities for space superiority. We build…
We believe general-purpose, generally-intelligent robots will be built in our lifetimes. Robots will work in our factories, move our goods, walk on our streets and eventually be in our homes. To build that future,…
Embedded systems software engineer on Google's Pixel Touch and Haptics Team, writing and optimizing low-level C/C++ firmware and Linux kernel drivers for touch controllers across Pixel devices.
ABOUT MDA SPACE Building the space between proven and possible, MDA Space is a trusted mission partner to the global space industry. A robotics, satellite systems and geointelligence pioneer with a 55-year+ story of…
Echodyne is seeking a Software Engineer II to design and develop high-assurance embedded software for radar systems. The role involves working with C++ on embedded Linux platforms to support radar signal processing and system control.
The Senior Firmware Engineer will design, develop, and maintain embedded software for regulated medical devices using C/C++ in RTOS and bare-metal environments. The role involves cross-functional collaboration on product architecture, connectivity solutions, and ensuring compliance with medical device standards like IEC 62304.
Leads a Shanghai hardware design team to develop high-speed Active Electrical Cables and Smart Cable Modules for AI infrastructure, while providing local customer engineering support to China-based hyperscalers and OEMs.
Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.
Principal Silicon Validation Engineer at Astera Labs in San Jose, CA designs and executes electrical tests to validate AI connectivity hardware, using PCIe, Ethernet, and CXL technologies.
Senior software engineer building diagnostics and manufacturing tools for high-speed datacenter hardware, using Python and embedded/Linux systems to validate and bring up AI connectivity boards.
Leads validation of AI connectivity chips and boards, designing tests to verify performance and compliance with high-speed interfaces like PCIe and Ethernet.
Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
Leads post-silicon validation and bring-up of high-speed SerDes (NRZ/PAM4) hardware, debugging mixed-signal issues (jitter, equalization, PLL/CDR) and automating test frameworks with Python/C++ to validate AI infrastructure connectivity chips for hyperscalers.
Designs and implements RTL for high-speed interconnect silicon (PCIe, CXL, Ethernet) that powers AI infrastructure, shepherding blocks from spec to tapeout.
Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.
Electrical engineer on Apple's iPad System EE team in Shenzhen, owning logic board and flex circuit design, power distribution, bringup/debug/validation, and factory NPI support from concept to ship.
Develops embedded firmware in C for STM32 microcontrollers, debugs board-level issues with oscilloscopes, and collaborates with hardware teams on motor-control systems for industrial and aerospace applications.
Senior embedded software engineer on Google's XR team, architecting and developing firmware/drivers in C/C++ for lightweight XR devices (smart glasses, headsets), optimizing real-time ML models on edge hardware for power, latency, and memory.
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable…
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