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Design Engineer at AccelerComm develops advanced IP, system, and board solutions for 5G wireless communications, using SystemVerilog, EDA tools, and hardware optimization techniques.
Designs and optimizes high-performance FPGA hardware for financial trading systems, using Verilog/SystemVerilog and modern FPGA toolchains, with a focus on low-latency interfaces like 100GbE and PCIe.
Design and verify integrated circuits for AR display systems, building UVM-based testbenches and using Siemens Questa for simulation and debug.
Principal IC Digital Design Engineer leads SoC micro-architecture, RTL development, and HW/SW co-design for advanced semiconductor solutions used in AI, cloud, and telecom.
Designs and implements FPGA logic for optical telecommunication products, collaborating with hardware and firmware teams to validate and optimize high-speed data transmission systems using Verilog/SystemVerilog and AMD/Xilinx or Altera tools.
Designs and leads the development of high-performance microcontrollers for edge AI applications, using Verilog/SystemVerilog, synthesis, and verification tools.
Designs and validates high-performance ASIC chips for Cisco's networking solutions using Verilog/SystemVerilog, CDC, lint, and formal verification, from architecture through tape-out and lab validation.
Leads digital IP design and architecture for NXP’s MCU/MPU portfolio, focusing on flash controllers, bus bridges, and ECC algorithms using Verilog/SystemVerilog and ARM cores.
Senior engineer building automation tools and methodologies to accelerate NVIDIA’s ASIC and SoC chip design flows, working with EDA vendors and RTL teams.
Principal engineer verifying advanced modem PHY IP for Blue Origin’s Terawave satellite network, ensuring high-speed wireless ASIC designs meet performance and integration requirements.
Sr. Manager - SOC Verification Location: India - Bangalore Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on…
Senior FPGA Engineer- ASIC/FPGA, Mission Systems (Hybrid) Location: US-PR-AGUADILLA-110 ~ Rd 110 N Km 28.8 ~ RD110 Time Type: Full time Job Description Date Posted: 2026-07-23 Country: United States of America…
Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities…
Design Verification Engineer in Cisco’s DFT team validates testability features for advanced networking and AI silicon using SystemVerilog/UVM, collaborating with cross-functional teams to ensure chip reliability and performance.
Hardware Engineer Intern - Summer 2027 Location: Chicago, United States Department: Development (Group) Our 10-week internship is your chance to experience life as a Hardware Engineer at IMC. You’ll have the support…
Hardware Engineer Location: Chicago, United States Department: Development (Group) IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next generation of custom ASICs that power our…
Graduate Hardware Engineer Location: Chicago, United States Department: Development (Group) Having the best technology drives our business. As a Hardware Engineer at IMC, you are responsible for spotting new…
FPGA Verification Engineer Level 3/4 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR…
FPGA Verification Engineer Level 5 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START:…
Senior Engineer - ASIC Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow With Us: About this opportunity: We are starting a new Silicon R&D center in…
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