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Designs and leads the architecture of safety-critical digital control systems for nuclear power plants, ensuring compliance with nuclear regulations and functional safety standards.
Designs and leads safety-critical digital control systems for nuclear power plants, ensuring compliance with nuclear regulations and translating requirements into robust system architectures.
Designs and leads the architecture of safety-critical digital control systems for nuclear power plants, ensuring compliance with nuclear regulations and standards while modernizing reactor safety features.
Designs and maintains performance models for next-gen AI/bitcoin chips, using C++/SystemC and Python to guide architecture decisions on tile arrays, NoC, and memory subsystems.
Builds and maintains a zero-touch automation pipeline for provisioning, validating, and managing Tower’s global fleet of trading servers using GitOps, Ansible, Python, and CI/CD.
Tower Research Capital is a leading quantitative trading firm founded in 1998. Tower has built its business on a high-performance platform and independent trading teams. We have a 25+ year track record of innovation…
Build and maintain the software that automates and monitors Tower’s GPU fleet, troubleshooting issues from applications down to the kernel to keep the firm’s trading infrastructure running at peak efficiency.
Design and verify mission-critical FPGA firmware for high-power satellites, implementing real-time control, networking, and RF systems in VHDL/SystemVerilog.
Develops real-time control software for high-speed aerospace systems, translating MATLAB/Simulink models into embedded C/C++ for motor control, safety interlocks, and hardware-in-the-loop testing in a fast-paced startup environment.
Design and implement motor controllers and power electronics for spacecraft payloads, using MATLAB, DSP, and FPGA to prototype flight-ready systems.
Design and maintain embedded firmware for high-speed networking and semiconductor products, including drivers, HAL, and validation tools using C/C++ and hardware interfaces.
Lead a team to set and enforce quality standards across product development, testing, and delivery for hardware, software, and mechanical systems in Singapore.
Designs and develops FPGA-based hardware boards, including PCB schematics, layout, and component selection, ensuring compatibility and performance for platform hardware systems.
Define the architecture and design methodologies for a new platform of digital compute and analog/mixed-signal semiconductor products, guiding global teams in microarchitecture and productization.
Design and verify complex silicon subsystems for Arm-based platforms using SystemVerilog/UVM, ensuring functionality, performance, and coverage closure.
Graduate trainee develops FPGA IP cores using HDL, RTL design, and verification, working with tools like Vivado/Quartus and collaborating on real-world FPGA-based system projects.
Designs and runs SystemVerilog/UVM testbenches to verify FPGA IP blocks and SoC designs, using coverage-driven methods and assertions to ensure first-pass silicon success.
Lead R&D projects for MACH™, Hitachi Energy’s control platform for HVDC/FACTS power systems, coordinating global teams to deliver hardware, software, and FPGA solutions that advance sustainable energy grids.
Lead embedded AI development for automotive ADAS/AD systems, optimizing deep-learning models for real-time deployment on AI SoCs and DSPs.
Design and verify FPGA-based systems using VHDL/SystemVerilog for aerospace/defense applications, collaborating with hardware and systems teams to meet DoD requirements.
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