Design Verification Engineer

About TI

Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world's brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We're committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!

About the Role:

Are you looking for a career at one of the leading semiconductor companies in the world? Texas Instruments (TI) is looking for a Digital Mixed-Signal (DMS) Design Engineer to join the team of enthusiastic engineers who develop highly complex mixed-signal devices for audio applications with industry-leading performance.

We are looking for a motivated and technically strong DMS Engineer to join our Audio Converters product development team. In this role, you will be responsible for the RTL design and implementation of digital blocks within complex mixed-signal audio converter chips. You will work closely with analog design, AMS verification, digital verification, systems and physical design engineers to develop robust, well-verified and silicon-ready digital implementations.

This role provides an opportunity to work on challenging digital design problems within a mixed-signal context, implement complex digital algorithms in RTL, understand the interaction between digital and analog domains, and contribute to products from architecture definition through tapeout and silicon bring-up.

Required Skills & Qualifications:

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related field.
• 3-5 years of hands-on experience in digital RTL design using Verilog and/or SystemVerilog.
• Strong digital design fundamentals: FSMs, FIFOs, pipelines, synchronizers, handshaking and arbitration logic.
• Solid understanding of clock domain crossing (CDC) and reset domain crossing (RDC) concepts and design techniques.
• Hands-on experience designing and verifying serial interfaces such as SPI, I²C, I²S, PDM or TDM.
• Experience implementing digital filter blocks (CIC, FIR, IIR) or other DSP-oriented digital designs.
• Familiarity with the RTL-to-GDSII design flow including synthesis, static timing analysis (STA) and sign-off concepts.
• Experience with RTL quality checks including linting (SpyGlass or equivalent) and CDC/RDC analysis tools.
• Ability to read and interpret timing reports and identify RTL-level root causes for timing violations.
• Basic understanding of mixed-signal design concepts: ADC/DAC architectures, signal chains and digital-analog interfaces.
• Familiarity with scripting languages such as Python, Perl or Tcl for design automation and flow development.

Additional preference

• Experience with audio converter products (ADC, DAC, CODEC, Class-D amplifiers) or audio SoC development.
• Knowledge of sigma-delta modulator architectures, oversampling and multi-stage decimation filter design.
• Experience with MATLAB or Simulink for fixed-point modeling or algorithm-to-RTL translation workflows.
• Exposure to UVM-based digital verification environments and co-simulation with analog models.
• Understanding of DFT concepts including scan architecture, ATPG and design-for-test best practices.
• Having contributed to RTL design from specification through tapeout and first-silicon bring-up.