<GPU>GPU HW Design Engineer
Description
Role and Responsibilities
•_x0001_Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem
•_x0001_RTL coding and deliver high quality scalable design to meet PPA requirements
•_x0001_Collaborate with verification team for feature description, testplan, and coverage closure
•_x0001_Assist DV engineers for debugging functional, performance, power test failures
•_x0001_Collaborate with synthesis and PD team for timing and area closure
•_x0001_Collaborate with power team to identify power saving opportunities and meet power target
•_x0001_Assist block team manager in strategy, planning, scope estimation, and progress reporting
Requirements
Requirement
•_x0001_MS or PhD degree or equivalent in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
•_x0001_5+ years of working experience on RTL design and overall ASIC design flow
•_x0001_Working experience of designing high throughput and low latency designs
•_x0001_Good knowledge of synthesis and PD flows
•_x0001_Good knowledge of different design techniques and their implications on physical design
•_x0001_Hands-on experience on SystemVerilog/VHDL/C/C++ and scripting programming
•_x0001_Hands-on knowledge/experience on pipeline design, digital signal processing, area/power optimization flow
•_x0001_Good teamwork and excellent interpersonal skills including both verbal and written communication
•_x0001_Strong problem solving, root causing and debugging skills
•_x0001_Good English reading and writing capabilities for technical documentation.
•_x0001_Able to work in a dynamic and fast changing environment
•_x0001_Preferred skills:
-Knowledge/experience on GPU pipeline (Shader, Texture, Geometry, Pixel, Raytracing, Memory etc.) and GPU architecture.
-Knowledge/experience on computer architecture, parallel computing or cache system.
-Knowledge/experience on floating point data processing.
-Experience collaborating with worldwide, cross-functional engineering teams.
Education: Master's Degree
