Senior Team Leader for Short Range Wireless VLSI system design
Posted Updated
Summary
Leads a team designing short-range wireless (Bluetooth/802.15.4) VLSI IP blocks: defines system architecture and sub-system specs, owns Verilog RTL through ASIC development under tight frequency/area/power targets, and supports customer IP integration. Core stack: Verilog/VHDL RTL, ASIC/FPGA flows, FPGA prototyping, Perl/Tcl/Python.
Senior Team Leader
for Short Range Wireless VLSI system design
Location : Bangalore
Experience:- 4 to 10 yrs
Years of Experience:- B.E in ECE with industrial experience of
8+ years
or
M.E
in VLSI/Signal processing/Electronics with minimum 6 years of industrial
experience
Must have skills:-
1. Excellent in micro-architecture and hands on RTL
design (Verilog/VHDL) of complex logic blocks and subsystems.
2. Expertise in ASIC or FPGA design flows.
3. Exposure to system level simulation and Verilog
based verification environment and scripting languages like Perl, Tcl or Python
4. Hands on prototyping experience on FPGA boards (like
Xilinx, Altera etc.)
5. Must be self-starter who can work independently or
in team environments, must be a team player, with the ability to co-ordinate
and work well with other cross-functional teams
6. Strong problem solving skills and excellent debugging
skills.
7. Excellent communication skills including verbal and
interpersonal skills, professional attitude and desire to succeed is required
8. Must have had prior experience in customer
interaction.
Good to have skills:-
1. Having worked on 2.4GHz systems like WLAN,
Bluetooth.
2. Exposure to Bluetooth Low Energy (BLE) or 802.15.4
is a big plus.
3. Exposure to fixed-point implementation.
4. Exposure to SoC level design.
5. Background in signal processing.
6. Exposure to hardware-software co-design, low power
design concepts.
7. Exposure to Intellectual Property development,
specifically having translated a specification to implementation.
8. Experience in core development of MAC (Medium Access
Control) for protocols like Ethernet or USB or Bluetooth or 802.15.4 or the
likes
Responsibilities:-
1. System architecture definition and realization of Bluetooth and 802.15.4 Wireless IP Blocks. This involves starting with industry standard specifications and defining sub-systems (e.g. State-Machines for protocol management, packet creation, encryption, Clocking, Power Management, interfacing to 3rd party RF Blocks and ARM cores, etc.)
1. System architecture definition and realization of Bluetooth and 802.15.4 Wireless IP Blocks. This involves starting with industry standard specifications and defining sub-systems (e.g. State-Machines for protocol management, packet creation, encryption, Clocking, Power Management, interfacing to 3rd party RF Blocks and ARM cores, etc.)
2. Create specifications for sub-systems on chip and
manage a team of engineers in development, testing and integration of various
sub-systems into the IP architecture
3. Ownership on a complete Verilog IP system targeting
ASIC, with tight frequency, area and power requirements.
4. Understand existing IP design and
Bluetooth15.4 specifications
5. Support customers with integration of IP into
customer ASIC design projects, in such areas as power optimization, clocking
and reset logic, memory interfaces, RF interface and system buses.
Domain:- VLSI design (RTL Front End)
Key words
RTL Design, Protocol (like
Ethernet, USB), FPGA, Wireless, Bluetooth, 802.15.4, Zigbee
Requirements
Note:
Keywords: RTL Design, Protocol (like Ethernet, USB),
FPGA, Wireless, Bluetooth, 802.15.4, Zigbee
Hands on RTL design (Verilog/VHDL) of complex
logic blocks and subsystems, on prototyping experience on FPGA boards (like
Xilinx, Altera etc.)
Experience in ASIC or FPGA design flows, python scripting,perl or TCL.
