SoC RTL (HDL) Design Engineer (Hyderabad)

SoC RTL (HDL) Design Engineer (Hyderabad) Company: Pqangels Technologies Job Location: Hyderabad, Telangana, India Employment Type: Full-time Experience Required: 5 - 11 years RTL Design Engineer | 5 -11 Years | Bengaluru Company: PQAngels Technologies Pvt Ltd Location: Bengaluru Experience: 5 -11 Years Employment Type: Full-Time About the Role PQAngels Technologies is looking for experienced RTL Design Engineers to join our semiconductor/VLSI engineering team. We are looking for candidates with solid hands-on experience in RTL development, Verilog/SystemVerilog, SoC/Subsystem design, NoC, and ASIC design flows. What You Will Work On Design and develop synthesizable RTL using Verilog/SystemVerilog. Convert microarchitecture specifications into RTL implementations. Own block-level RTL design, development, and debugging. Work on SoC/Subsystem and NoC-based designs. Perform RTL quality checks, including Lint and CDC. Support synthesis and resolve synthesis-related issues. Collaborate with DV, Physical Design, and SoC Integration teams. Analyze and optimize designs for Performance, Power, and Area (PPA). Reg Map Integrations, PHY Integrations Participate in design reviews and technical discussions. Support customer-facing technical discussions when required. Key Skills Must Have: Verilog SystemVerilog RTL Design Microarchitecture ASIC/VLSI Design Flow Synthesis Lint & CDC RTL Debugging Good to Have: NoC / Subsystem CPU / GPU architecture DDR PCIe USB Ethernet TCL / Python / Perl scripting Tools Synopsys Design Compiler SpyGlass VC SpyGlass Education BE/BTech/ME/MTech in ECE, Electrical, Electronics, VLSI, Microelectronics, or a related discipline. Ideal Candidate We are looking for engineers who have strong RTL fundamentals, hands-on ASIC design experience, good debugging skills, and the ability to work collaboratively across RTL, DV, PD, and SoC teams. Interested candidates can apply with their updated profile. .