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An ASIC digital engineer specializing in FPGA prototyping, emulation, and system-level debugging to support platform bring-up, hardware/software co-verification, and end-user collaboration.
Senior Staff VLSI Design Engineer coding C++ and SystemC functional models and testbenches for memory/storage products, validating models using SystemC/SV/UVM, debugging firmware issues, and mentoring junior engineers.
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Top Secret TRAVEL: Yes, 25% of the Time Description At Northrop Grumman, our employees have incredible…
RELOCATION ASSISTANCE: No relocation assistance available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: Secret TRAVEL: Yes, 25% of the Time Description At Northrop Grumman, our employees have incredible…
Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to…
Sr. Staff ASIC Design Engineer responsible for microarchitecture and RTL design of high-performance AI inference ASICs using Verilog/SystemVerilog, integrating CPU and third-party IPs, and collaborating with physical design and verification teams.
Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of…
Designs and implements high-performance semiconductor chips for AI infrastructure, focusing on physical design flows, signoff, and automation in advanced process nodes.
Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.
Designs and verifies next-gen ASIC/FPGA SoCs using SystemVerilog/UVM, ensuring bug-free silicon by collaborating across global teams.
Staff Digital Design Engineer responsible for all aspects of digital design in 3D NAND Flash memory, including micro architecture, RTL design in Verilog, verification, synthesis, DFT, and timing analysis from RTL to GDSII.
Designs and implements high-performance, low-power memory logic from netlist to GDSII, focusing on timing closure, power integrity, and manufacturability in advanced process nodes.
Company: Qualcomm Israel Ltd. Job Area: Engineering Group, Engineering Group > Modem Technologies General Summary: S enior Staff RTL Design Engineer - Haifa or Hod HaSharon As an RTL Design Engineer, you would be…
The Senior Staff Digital Design Engineer will lead the design, implementation, and verification of DSP algorithms and digital control logic for audio processing within ASIC systems. This role involves the full ASIC design flow, from specification to silicon bring-up, utilizing expertise in digital signal processing and mixed-signal integrated circuits.
We made history and now we work to transform the future – for our customers, our communities and our families. You'll see your work on the road every day, helping people move freely and pursue their dreams. At…
Oversees SoC/MCU hardware development from concept to mass production, managing cross-functional teams, timelines, budgets, and risks to ensure on-time delivery and efficiency improvements.
Leads FPGA fabric design optimization and research for AMD’s Adaptive & Embedded Computing Group, focusing on programmable logic improvements, yield enhancement, and collaboration with silicon teams to advance future product architectures.
Design and build data center hardware systems from concept through high-volume manufacturing, leading system/hardware design and validation for Google's Platforms Infrastructure Engineering team.
Lead the architecture and integration of sensor systems for autonomous delivery drones, defining performance models and guiding hardware/software teams to meet strict SWaP-C constraints.
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