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We are looking for an enthusiastic PCIe Design Verification Engineer with 7–8 years of proven professional experience to join our IP Design team. As a PCIe Design Verification Engineer, you will be part of a highly…
We are looking for experienced Physical Design Engineers with 7–8 years of proven professional experience to join our IP Design team. As a Physical Design Engineer, you will be part of a highly competent team…
We are looking for an enthusiastic UAL Design Verification Engineer with 4–5 years of proven professional experience to join our IP Design team. As a UAL Design Verification Engineer, you will be part of a highly…
Leads ASIC physical design for Cisco’s networking hardware, optimizing chip layouts, managing cross-functional teams, and driving SoC execution from concept to release in advanced process nodes.
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
Date Posted: 2026-09-03 Country: United States of America Location: US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements:…
Date Posted: 2026-09-03 Country: United States of America Location: US-TX-MCKINNEY-513WC ~ 2501 W University Dr ~ WING C BLDG Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements:…
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Next Generation, High-Speed, Memory and Cache Controller Design Team is looking for a Senior…
Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable…
A senior ASIC design engineer who designs, verifies, brings up, and debugs digital subsystems in electro-optical SoCs for Ayar Labs' co-packaged optics that move data for AI systems. Day to day: RTL in Verilog/SystemVerilog, testbenches, timing constraints and documentation, and Python-driven silicon bring-up.
Owns and scales the front-end CAD/design automation flows for Ayar Labs' ASIC and SoC teams in Bengaluru: building Python/Tcl/Shell/Make tooling for lint, CDC/RDC, regressions, and signoff readiness, supporting Synopsys/Cadence/Siemens EDA deployments, and championing AI-assisted CAD agents and workflows.
Head of Business Development - Taiwan Location: Hsinchu, Taiwan (with regular travel to Taepei, Taichung, Tainan and periodic travel to San Jose, CA) Ayar Labs is shattering AI data bottlenecks by moving data at the…
Sr. Staff Engineer designing and debugging digital subsystems for Ayar Labs' electro-optical ASICs (co-packaged optics that move AI data over light). Day to day: writing RTL in Verilog/SystemVerilog, building testbenches, defining timing constraints, and doing silicon bring-up/debug with Python, C/C++, and firmware — on-site in San Jose.
Ayar Labs is hiring a Principal Design Verification Engineer in Bengaluru to lead verification strategy for its next-generation silicon photonic (co-packaged optics) chip. The role involves architecting scalable UVM testbenches, setting verification methodology, debugging complex hardware issues, automating regressions, and mentoring engineers using SystemVerilog/UVM, protocol knowledge (PCIe, AMB
Ayar Labs is hiring a Principal DFT Engineer in Bengaluru (on-site, flexible hours) to lead Design-for-Test architecture, implementation, and silicon bring-up for electro-optical SoCs and chiplet-based systems. Core work spans scan/ATPG, MBIST/LBIST, JTAG, silicon debug, and production test flows with Python/Tcl automation.
Senior ASIC Design Verification Engineer at Ayar Labs (Bengaluru, on-site) doing pre-silicon verification of complex SoCs with digital and mixed-signal blocks: building SystemVerilog/UVM testbenches, test plans and coverage closure for SerDes, parallel-link and on-chip interconnect IP within a small startup IC design team.
Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring…
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and integration of digital systems in TetraMem’s AI accelerators. You’ll contribute to RTL design, simulations, and…
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