Phison Electronics Corp_群聯電子股份有限公司

前瞻數位IC設計流程工程師0200

1.Frontend design flow and quality check development. 2,Power domain plan and UPF/IEEE1801 power internt edit. 3.Advanced design methodology study and evaluation. 4.Interact with RTL & APR and provide them with…

數位IC設計工程師8110

1. 數位電路架構開發及驗證 ( Verilog / System Verilog / UVM) 2. 熟悉 CPU 硬體架構 / CPU 效能分析 3. FTL ( Flash Transfer Layer) algorithm IP 設計 4. 熟悉 AXI / AHB protocol，bus protocol IP 設計

Uvm Verilog

數位IC設計工程師8601

職缺有分DE及DV DE的部分: 1. Digital IP design. Develop/integrate high speed interface design 2. Famlilar with PCIe is a plus 2. FPGA is a plus 3. familiar with UVM is a plus DV的部分: 1. Digital design verification .Co-work with…

FPGA PCIe Uvm Verilog

數位IC設計工程師0300

【About the Team】 We are leading the industry in UFS 4.0 and pioneering the development of UFS 5.0. We are looking for an engineer to help us build the world's most advanced UFS controllers, pushing the limits of…

FPGA Prototyping Rtl Uvm

類比IC設計工程師0501

1. High Speed IO/transceiver circuit designs on DDR4/5 PHY, flash PHY. 2. Power analog circuit designs on PMIC, DC2DC converter, LDO. 3. Analog circuit design on various functional analog IPs like ADC, PLL, DAC

數位IC設計工程師0200

1.SSD RTL 開發 2.Simulation FPGA驗證 3.Formal,COC,STA…

類比混合訊號IC設計/高速介面IC設計工程師/Serdes IC design(竹南)

Analog/Mixed signal IC design & architecture for SerDes, Adaptive Equalizer (CTLE/FFE/DFE), CDR, PLL, PHY, Transmitter, Receiver, RF , wide-band, high frequency amplifier, LNA, TIA, PA Project example: SATA, USB, PCIe,…

PCIe SerDes

SOC 數位IC驗證工程師(竹南/竹北)

1. Built up block/SoC-level verification environment using SystemVerilog/UVM, and simulation patterns generation. 2. SoC integration, bus fabric/high speed peripherals connection verification. 3. SoC clock, reset,…

Rtl SystemVerilog Uvm

Retimer 數位IC設計工程師

1. Digital design/integration/verification 2. Familiar with interface protocols such as PCI Express, SuperSpeed USB, etc. 3. Experiences in mixed signal design is a plus.

數位IC設計工程師8600

1.高速週邊IO之數位電路開發2.ncverilog程式設計、模擬3.FPGA驗證4.協助IP應用/授權之除錯與驗證 5. Analog modeling

類比混合訊號IC設計/高速介面IC設計工程師/Serdes IC design(竹南)0201

Analog / mixed-signal IC design and architecture for SerDes RX_AFE (CTLE/VGA), TI-ADC (time-interleaved ADC), high-speed DAC transmitter, oscillator and clocking Project experience: DSP-based SerDes, PCIe 6/7, Ethernet…

Ethernet PCIe SerDes

電子硬體系統工程師

1.PCB板子設計製作 - 開發、測試、生產所需的全系列板子 2.跨部門技術支援、溝通協調 -資訊收集/評估/量測/驗證/Debug/採買 3.安排項目執行 - 新知Study、板子/料件管理、AI導入、程式檢查、儀器修復及其他部門所需事項

PCIe 應用工程師

1.Retimer & PCIe Controller IP & PCIe PHY IP相關應用問題分析除錯。 2.協助專案FW解決Retimer & PCIe Controller IP & PCIe PHY IP使用上的問題。 3.依據IP使用者反饋以及應用問題分析結果，提出IP改善方案。

PCIe

High-Speed DSP SerDes 演算法工程師0201

Cadence Virtuoso Machine Learning MATLAB Python SerDes +1 skills

1. Develop and optimize TED, EQ (FFE/DFE/MLSD), and ADC Calibration algorithms for 200G+ SERDES designs 2. Build algorithm specifications and perform fixed-point analysis; verify performance using MATLAB, Python, and…

Memory IP Design engineer

1. Customizate SRAM IP design for Phison Project. 2. Memory/SRAM circuit simulation and design verification. 3. Familiar with Tcl coding for SRAM compiler tiling engine. 4. Memory/SRAM yield improvement & test IP…

Tcl Verilog

【約聘】FPGA測試副工程師

1. 協助架設FPGA平台 2. 協助架設及維護FPGA周邊設備 3. 配合管理實驗室及其他臨時交辦事項

SRAM digital design flow RD engineer

1.Create digital SRAM design flow, including RTL coding, synthesis and floorplan consideration. 2.Analysis and provide the best PPA SRAM selection flow for project usage.

Rtl

車規智能應用工程師

Confluence Iso 26262 Jira

依學經歷以下列其中之一為工作內容 1.技術類: a. ISO 26262 Part 5/7;21434;61508 相關流程與文件執行 b. AI的工具開發協助優化流程 c. 安全硬體相關討論 2.流程類: a. 協助project leader管理開發流程相關事務(PCC) b. 操作流程工具(JIRA/confluence) c. 修改管理SOP文件(進版、改版、申請發行)

NVM電路設計工程師