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Build and test diagnostics and manufacturing tests for high-speed networking hardware, using C/Python on Linux to validate ASIC-based boards and support customer deployments.
Verify next-gen PCIe controller subsystems for AMD’s SoCs, using UVM, SystemVerilog, and low-power flows to ensure performance and power targets for AI, gaming, and server chips.
Design and optimize FPGA/SoC solutions for high-performance digital signal processing and RF applications using Xilinx devices and Vivado.
Develop and maintain embedded Linux BSPs, secure boot chains, and device drivers for defense-grade compute modules, taking boards from first power-up to flight-ready systems.
Senior engineer running signal and power integrity simulations for high-speed interfaces in autonomous-vehicle hardware, using tools like HyperLynx and ANSYS.
Role Summary Own the end-to-end PCIe system design for an NVMe SSD product line across client laptops and enterprise servers, from PHY/MAC review through ASIC/SoC integration, PCIe SFR/register analysis, and firmware…
Lead product strategy for Google’s host networking stack powering AI training and inference, collaborating with engineers to deliver high-performance libraries and telemetry for TPU, GPU, and standard compute systems.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Lead firmware development for Direct Flash Module (DFM) SSDs, owning the roadmap, PCIe integration, and NAND management to deliver the world’s fastest enterprise storage solutions.
Designs and implements digital signal processing algorithms in MATLAB/Simulink or Python, converts them to fixed-point HDL for FPGA deployment, and collaborates with hardware teams to bring up and tune DSP-based systems across industries like communications, aerospace, and medical devices.
Design high-speed electronic systems and PCBs for clients, collaborating with FPGA, software, and SI teams to deliver robust hardware from concept to validation.
Lead FPGA design and verification for aerospace/defense avionics, writing VHDL/SystemVerilog, ensuring DO-254 compliance, and mentoring small teams.
Lead FPGA verification for safety-critical avionics under DO-254, defining test strategies and ensuring FAA/EASA certification readiness with UVM, SystemVerilog, and VHDL.
Design and verify PCIe interconnect IP for AMD’s GPUs, APUs, servers, and consoles using UVM/SystemVerilog, collaborating with global teams.
Design and own the on-chip interconnect fabric and high-speed I/O subsystems for AI-driven ASICs, implementing AMBA-compliant NoC routers, crossbars, and bridges to ensure low-latency, high-bandwidth data movement in production silicon.
Lead hardware board design for next-gen routing products, shepherding designs from architecture through production while coordinating cross-functional teams.
Develops Linux kernel drivers and diagnostics for Cisco’s network switches and routers, ensuring hardware reliability and performance in high-speed networking environments.
Lead FPGA design and verification for Thales’ hardware systems, writing VHDL RTL, building test benches, and optimizing designs to meet DO-254 requirements.
Drive the product roadmap and GTM for Broadcom’s PCIe switch line, aligning AI/ML server architectures with market needs and collaborating with hyperscalers and OEMs.
Manage a team of 10–15 embedded software engineers developing real-time communications systems for defense programs like F-22, F-35, and Link16 radios.
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