Velaura AI, Inc.

NewBe an early applicant On-siteAPACSenior

yesterday

Senior Engineer CAD Pre Silicon Front End

AI Automation CAD Distributed Computing FPGA +6 skills

You will own front-end automation from RTL entry through DFT and implementation handoff. You will maintain design, verification, emulation, and FPGA prototyping flows; build AI-assisted tools; manage tool availability;…

NewBe an early applicant On-siteAPAC

yesterday

AI Systems Architect Models and Hardware Co Design

AI Deep Learning JAX Machine Learning Model Deployment +2 skills

You will evaluate modern AI model architectures, training and inference characteristics, and workload requirements. You will translate model requirements into efficient hardware implementations, develop performance…

5 days ago

RTL Designer

New On-siteAPAC

AI Rtl SystemVerilog Verilog

Designs, implements, and optimizes RTL (Verilog/SystemVerilog) for core SoC components — compute engines, memory subsystems, interconnect fabrics, DMA engines, and power-management logic — collaborating on microarchitecture, hardware-software co-design, and performance/power/area tradeoffs alongside verification and physical design teams.

Senior Design Verification Engineer

On-siteAPACSenior

C++ FPGA Prototyping QoS Root Cause Analysis +2 skills

Develops and executes verification strategies and environments for complex SoC hardware — building UVM/SystemVerilog testbenches, assertions, formal and emulation flows, verifying compute, memory, and interconnect blocks, and supporting emulation, FPGA prototyping, pre-silicon bring-up, and post-silicon debug.

Design Verification Engineer CPU

On-siteAPAC

C++ FPGA Prototyping Root Cause Analysis SystemVerilog +1 skills

Verification engineer for a custom CPU: owns functional verification from test planning through coverage closure — building SystemVerilog/UVM environments, writing C/C++ instruction-level stimulus, verifying memory ordering, coherence, and performance, and supporting emulation, FPGA prototyping, and pre-silicon software bring-up.

Design Verification Engineer AI Accelerator

On-siteAPAC

AI C++ LLM Python Quantization +2 skills

Owns verification of custom AI accelerator hardware (matrix and vector compute engines): builds SystemVerilog/UVM test and coverage environments, develops C/C++/Python reference models for GEMM/GEMV, verifies numerical precision and performance, and supports emulation and pre-silicon bring-up.

Design Verification Engineer

On-siteAPAC

C++ FPGA Prototyping QoS Root Cause Analysis +2 skills

Design Verification Engineer at Velaura AI in Bangalore developing verification strategies and environments for complex SoC hardware: building SystemVerilog/UVM and C/C++ testbenches, verifying compute engines, memory subsystems, and interconnects, and supporting emulation, FPGA prototyping, and post-silicon debug.

last month

CAD Back-end Lead

Open 35d On-siteAPACLead

Agentic AI AI Ansys Asic Bash +12 skills

You will build, integrate, qualify, release, and support CAD flows across custom design, physical implementation, and physical verification. You will develop reusable frameworks, automate regression testing and quality…

Open 40d On-siteAPAC, North America

last month

SoC Design Verification Engineer

You will plan and execute system-level SoC verification, build simulation environments, and verify boot, security, clock, reset, low-power, IO, and memory behavior. You will run CDC and RDC analysis, assess…

C++ Firmware PCIe QoS SystemVerilog +1 skills

Open 71d On-siteAPAC, North AmericaPrincipal

2 months ago

Custom Circuit Design (Sr. Staff / Principal)

Leads the design and optimization of high-performance, low-power standard cell libraries and custom digital circuits, including transistor-level innovation, arithmetic block architecture, and circuit verification across PVT corners. Focuses on reliability sign-off, low-power innovations, and mentoring engineers in advanced CMOS technologies.

Automation CAD Cadence Virtuoso Cmos Perl +2 skills

Open 71d On-siteAPACPrincipal

3 months ago

Physical Design Engineer (Staff / Sr. Staff / Principal)

AI Automation CAD GPU Perl +3 skills

Drive physical implementation and sign-off of critical blocks for next-generation AI and high-performance computing silicon, owning complex designs from RTL to GDSII across synthesis, floorplanning, place and route,…