Velaura AI, Inc.

5 days ago

RTL Designer

New On-siteAPAC

AI Rtl SystemVerilog Verilog

Designs, implements, and optimizes RTL (Verilog/SystemVerilog) for core SoC components — compute engines, memory subsystems, interconnect fabrics, DMA engines, and power-management logic — collaborating on microarchitecture, hardware-software co-design, and performance/power/area tradeoffs alongside verification and physical design teams.

Senior Design Verification Engineer

On-siteAPACSenior

C++ FPGA Prototyping QoS Root Cause Analysis +2 skills

Develops and executes verification strategies and environments for complex SoC hardware — building UVM/SystemVerilog testbenches, assertions, formal and emulation flows, verifying compute, memory, and interconnect blocks, and supporting emulation, FPGA prototyping, pre-silicon bring-up, and post-silicon debug.

Design Verification Engineer CPU

On-siteAPAC

C++ FPGA Prototyping Root Cause Analysis SystemVerilog +1 skills

Verification engineer for a custom CPU: owns functional verification from test planning through coverage closure — building SystemVerilog/UVM environments, writing C/C++ instruction-level stimulus, verifying memory ordering, coherence, and performance, and supporting emulation, FPGA prototyping, and pre-silicon software bring-up.

Design Verification Engineer AI Accelerator

On-siteAPAC

AI C++ LLM Python Quantization +2 skills

Owns verification of custom AI accelerator hardware (matrix and vector compute engines): builds SystemVerilog/UVM test and coverage environments, develops C/C++/Python reference models for GEMM/GEMV, verifies numerical precision and performance, and supports emulation and pre-silicon bring-up.

Design Verification Engineer

On-siteAPAC

C++ FPGA Prototyping QoS Root Cause Analysis +2 skills

Design Verification Engineer at Velaura AI in Bangalore developing verification strategies and environments for complex SoC hardware: building SystemVerilog/UVM and C/C++ testbenches, verifying compute engines, memory subsystems, and interconnects, and supporting emulation, FPGA prototyping, and post-silicon debug.

Open 39d On-siteNorth AmericaLead

last month

SoC Design Verification Lead

C++ PCIe SystemVerilog Uvm

You will own the SoC verification strategy, plan, architecture, and execution. You will lead verification engineers, coordinate system-level verification areas, drive coverage closure and tape-out readiness, report…

Open 39d On-siteAPAC, North America

last month

SoC Design Verification Engineer

You will plan and execute system-level SoC verification, build simulation environments, and verify boot, security, clock, reset, low-power, IO, and memory behavior. You will run CDC and RDC analysis, assess…

C++ Firmware PCIe QoS SystemVerilog +1 skills

Open 39d On-siteNorth AmericaSenior

last month

Senior Engineer CAD Pre-Silicon Front End

AI CAD FPGA Grafana Linux +5 skills

You will own RTL, register-generation, design-verification, emulation, and FPGA-prototyping flows. You will build AI-assisted tooling, maintain reliable engineering workflows, improve productivity, and partner on DFT…

Open 59d On-siteNorth America

2 months ago

Design Verification Engineer – CPU

C++ FPGA Prototyping Root Cause Analysis SystemVerilog +1 skills

Own pre-silicon verification of custom CPU units (fetch, decode, load-store, caches) by building SystemVerilog/UVM environments, developing instruction-level stimulus, running regressions, and supporting FPGA/emulation bring-up.

Open 59d On-siteNorth AmericaLead

2 months ago

Design Verification Engineer – AI Accelerator Lead

AI C++ LLM Neural Networks ONNX +5 skills

Own verification for custom AI acceleration units—translating microarchitecture into test/coverage plans, building SystemVerilog/UVM environments, developing GEMM/GEMV reference models, and supporting pre-silicon bring-up.

Open 69d On-siteNorth AmericaSenior

2 months ago

Senior Design Verification Engineer – Physical AI Compute

AI Automation C++ Firmware FPGA +7 skills

Design and execute verification plans for a Physical AI SoC using SystemVerilog/UVM, C/C++, assertions, and emulation to validate compute engines, memory, and interconnects.

Open 74d On-siteNorth America

3 months ago

RTL Designer – Physical AI Compute

Design and optimize RTL for AI-focused System-on-Chip components, focusing on performance, power, and area while collaborating on verification and physical design.

AI SystemVerilog Verilog

Open 69d On-siteNorth America

3 months ago

Design Verification Engineer – Physical AI Compute