Velaura AI, Inc.

NewBe an early applicant On-siteAPACSenior

yesterday

Senior Engineer CAD Pre Silicon Front End

AI Automation CAD Distributed Computing FPGA +6 skills

You will own front-end automation from RTL entry through DFT and implementation handoff. You will maintain design, verification, emulation, and FPGA prototyping flows; build AI-assisted tools; manage tool availability;…

NewBe an early applicant On-siteAPAC

yesterday

AI Systems Architect Models and Hardware Co Design

AI Deep Learning JAX Machine Learning Model Deployment +2 skills

You will evaluate modern AI model architectures, training and inference characteristics, and workload requirements. You will translate model requirements into efficient hardware implementations, develop performance…

5 days ago

RTL Designer

New On-siteAPAC

AI Rtl SystemVerilog Verilog

Designs, implements, and optimizes RTL (Verilog/SystemVerilog) for core SoC components — compute engines, memory subsystems, interconnect fabrics, DMA engines, and power-management logic — collaborating on microarchitecture, hardware-software co-design, and performance/power/area tradeoffs alongside verification and physical design teams.

Senior Design Verification Engineer

On-siteAPACSenior

C++ FPGA Prototyping QoS Root Cause Analysis +2 skills

Develops and executes verification strategies and environments for complex SoC hardware — building UVM/SystemVerilog testbenches, assertions, formal and emulation flows, verifying compute, memory, and interconnect blocks, and supporting emulation, FPGA prototyping, pre-silicon bring-up, and post-silicon debug.

Design Verification Engineer CPU

On-siteAPAC

C++ FPGA Prototyping Root Cause Analysis SystemVerilog +1 skills

Verification engineer for a custom CPU: owns functional verification from test planning through coverage closure — building SystemVerilog/UVM environments, writing C/C++ instruction-level stimulus, verifying memory ordering, coherence, and performance, and supporting emulation, FPGA prototyping, and pre-silicon software bring-up.

Design Verification Engineer AI Accelerator

On-siteAPAC

AI C++ LLM Python Quantization +2 skills

Owns verification of custom AI accelerator hardware (matrix and vector compute engines): builds SystemVerilog/UVM test and coverage environments, develops C/C++/Python reference models for GEMM/GEMV, verifies numerical precision and performance, and supports emulation and pre-silicon bring-up.

Design Verification Engineer

On-siteAPAC

C++ FPGA Prototyping QoS Root Cause Analysis +2 skills

Design Verification Engineer at Velaura AI in Bangalore developing verification strategies and environments for complex SoC hardware: building SystemVerilog/UVM and C/C++ testbenches, verifying compute engines, memory subsystems, and interconnects, and supporting emulation, FPGA prototyping, and post-silicon debug.

CAD Back-end Lead

Open 35d On-siteAPACLead

Agentic AI AI Ansys Asic Bash +12 skills

You will build, integrate, qualify, release, and support CAD flows across custom design, physical implementation, and physical verification. You will develop reusable frameworks, automate regression testing and quality…

Open 40d On-siteNorth AmericaLead

SoC Design Verification Lead

C++ PCIe SystemVerilog Uvm

You will own the SoC verification strategy, plan, architecture, and execution. You will lead verification engineers, coordinate system-level verification areas, drive coverage closure and tape-out readiness, report…

Open 40d On-siteAPAC, North America

SoC Design Verification Engineer

You will plan and execute system-level SoC verification, build simulation environments, and verify boot, security, clock, reset, low-power, IO, and memory behavior. You will run CDC and RDC analysis, assess…

C++ Firmware PCIe QoS SystemVerilog +1 skills

Open 40d On-siteNorth AmericaSenior

Senior Engineer CAD Pre-Silicon Front End

AI CAD FPGA Grafana Linux +5 skills

You will own RTL, register-generation, design-verification, emulation, and FPGA-prototyping flows. You will build AI-assisted tooling, maintain reliable engineering workflows, improve productivity, and partner on DFT…

Office Admin / Receptionist

On-siteNorth America

You will manage reception, visitor access, mail, shared spaces, supplies, vendors, and workplace inventory. You will support interviews, meetings, events, onboarding, offboarding, and executive administration while…

Open 48d On-siteNorth America

Director of IT Infrastructure and Operations

AWS Azure CI/CD Cloud DLP +16 skills

Owns IT infrastructure and operations end to end at an AI silicon company: running Linux HPC, CI/CD build farms, and hybrid Azure/GCP/AWS and on-prem environments for semiconductor engineering workloads, while establishing security controls (SOC 2/ISO 27001 readiness) and leading the IT team, budgets, vendors, and service desk.

Open 60d On-siteNorth America

Design Verification Engineer – CPU

C++ FPGA Prototyping Root Cause Analysis SystemVerilog +1 skills

Own pre-silicon verification of custom CPU units (fetch, decode, load-store, caches) by building SystemVerilog/UVM environments, developing instruction-level stimulus, running regressions, and supporting FPGA/emulation bring-up.

Open 60d On-siteNorth AmericaLead

Design Verification Engineer – AI Accelerator Lead

AI C++ LLM Neural Networks ONNX +5 skills

Own verification for custom AI acceleration units—translating microarchitecture into test/coverage plans, building SystemVerilog/UVM environments, developing GEMM/GEMV reference models, and supporting pre-silicon bring-up.

Open 69d On-siteNorth AmericaSenior

Senior Design Verification Engineer – Physical AI Compute

AI Automation C++ Firmware FPGA +7 skills

Design and execute verification plans for a Physical AI SoC using SystemVerilog/UVM, C/C++, assertions, and emulation to validate compute engines, memory, and interconnects.

Open 71d On-siteAPAC, North AmericaPrincipal

Custom Circuit Design (Sr. Staff / Principal)

Leads the design and optimization of high-performance, low-power standard cell libraries and custom digital circuits, including transistor-level innovation, arithmetic block architecture, and circuit verification across PVT corners. Focuses on reliability sign-off, low-power innovations, and mentoring engineers in advanced CMOS technologies.

Automation CAD Cadence Virtuoso Cmos Perl +2 skills

Open 69d On-siteNorth AmericaContractPrincipal

3 months ago

Principal AI SoC Runtime Software Architect

AI API C++ Embedded Linux Firmware +2 skills

Own the software architecture for a heterogeneous AI SoC and define the end-to-end runtime across sensor ingest, preprocessing, AI inference, postprocessing, and application delivery. Coordinate workloads and data…

Open 75d On-siteNorth America

3 months ago

RTL Designer – Physical AI Compute